In the system of U.S. Pat. No. 4,086,862, no use is made of the usual addressing counter customarily employed for read-out of the ROM or RAM which stores the stitch-control data for the plurality of selectable stitch-patterns which the system is to afford. Instead, operator selection of one of the available stitch-patterns serves to address the initial ROM storage location for that pattern. The thusly addressed storage location stores bits determinative of the transversely shifted position to be assumed by the transversely displaceable needle bar of the sewing machine, and also bits determinative of the amount by which cloth is to be fed forwards or backwards in going from the first to the second needle penetration location of the stitch-pattern, and furthermore bits which are determinative of the address of the second ROM storage location for that pattern.
In that way, after the initial storage location of the selected pattern has been externally addressed, the address locations for the subsequent stitches of the selected stitch-pattern are each determined, at least in part, by next-address data stored at each addressed storage location. Accordingly, after addressing of the initial storage location, subsequent addressing occurs, so to speak, from inside out, the ROM furnishing its own next-address signals, or at least contributing to their establishment. As a result, it ceases to be necessary for the successive storage locations of a single one of the stitch patterns to have numerically consecutive addresses such as are needed when read-out of the ROM is controlled, as in prior art, by an addressing counter which produces address signals in simple numerical order. Thus, for example, if a ROM, and its cooperating circuitry, has originally been sectored into ten storage sectors, each consisting of e.g. sixteen consecutive storage locations, for the storage of ten selectable patterns, it becomes possible to substitute a ROM whose e.g. ten patterns are not of sixteen stitches or storage locations each but instead various as to number of storage locations. For example, a simple stitch pattern which requires only three storage locations can be stored in the first three storage locations of the first of the ten storage sectors. In order that the remaining thirteen storage locations of the first storage sector not be wasted, a more complicated stitch pattern which requires twenty storage locations can be stored, to the extent of sixteen of its stitches, in the sixteen storage locations of the second storage sector, with the data for its remaining four stitches stored in otherwise unutilized ones of the thirteen empty storage locations of the first sector; and so forth. This reorganization of stored stitch-pattern control data can be implemented, in the extreme case, without any modification whatsoever of the peripheral circuitry which cooperates with the ROM. The ability to replace one pattern ROM with another of different data organization, without any need to respect predetermined storage sectors of fixed size, can result in valuable flexibility, whether at the level of a changeover capability for existing machines, or at the manufacturer's level when new and different stitch-patterns are to be offered on an existing product line.
Although the importance of such flexibility and freedom of organization and reorganization is considerable, it does require that each addressed storage location of the pattern memory contain additional bits, i.e., next-address bits in addition to true pattern-control bits. Relative to problematic instances of pattern assignment or pattern reorganization, especially those involving storage of both few-stitch and many-stitch patterns, the need for additional bits may not prevent an actual decrease in the total number of bits which the pattern memory need store. However, relative to the ideal case (e.g., where all patterns are of identical and numerically convenient stitch-number and, due to lack of pattern-flexibility worries, a mere addressing counter can be used), the fact remains that in principle additional bit-storage capability is required, and reduction in such bit-storage capability is very desirable.